An equalizer circuit is used to compensate for losses when transmission lines and cables having losses are used for data exchanges between LSIs, between devices or circuit blocks within a chip, between boards or housings, etc. FIG. 1 is a drawing illustrating an example of the configuration of a related-art equalizer circuit. An equalizer circuit 12 of FIG. 1 receives a data waveform from a transmission line 10, and supplies a corrected data waveform to a data detection circuit 11. The equalizer circuit 12 is an analog derivative equalizer, which includes an element 13 for outputting a received signal as it is, a first derivative element 14, a second derivative element 15, an amplifier 16 having gain A0, an amplifier 17 having gain A1, an amplifier 18 having gain A2, and an adder 19. The equalizer circuit 12 adds up the outputs of the elements 13 through 15 after amplification according to their respective gains, thereby enhancing and correcting changes in the input signal.
FIG. 2 is a drawing illustrating a unit pulse response of the equalizer circuit 12. The horizontal axis represents time, and the vertical axis represents signal amplitude. The output of the transmission line and the output of the equalizer circuit 12 are illustrated as observed when a pulse having a width of 1 unit time length and having an amplitude of 1 is input into the transmission line 10. A rise in a waveform output from the transmission line is gentle. Due to a length exceeding one unit, inter-symbol interference is large. The output of the equalizer circuit, on the other hand, has enhanced signal changes, so that its rise is steep, resulting in small inter-symbol interference.
In the configuration illustrated in FIG. 1, equalizing factors A0, A1, and A2 of the equalizer circuit 12 may be adjusted in response to the characteristics of the transmission line 10, thereby ensuring a sufficient data amplitude that is properly receivable despite changes in the characteristics of the transmission line 10. Adaptive equalization is a technology that changes equalizing factors in response to changes in the characteristics of the transmission line 10.
FIG. 3 is a drawing illustrating another example of the configuration of a related-art equalizer circuit. The equalizer circuit of FIG. 3 includes transistors 21 through 28, a variable resistor 29, resistors 30 through 32, and a capacitor 33. The resistance of the variable resistor 29 is adjusted in response to the setting of equalizing factor EQ thereby to adjust the direct current gain of a differential amplifier that is comprised of the transistors 21 and 22, the variable resistor 29, the capacitor 33, and the resistors 31 and 32. While high frequency characteristics are maintained by a capacitive coupling of the capacitor 33, the resistance of the variable resistor 29 is increased to lower the direct current gain.
FIG. 4 is a drawing illustrating an example of the frequency characteristics of the equalizer circuit illustrated in FIG. 3. The horizontal axis represents signal frequency, and the vertical axis represents the gain of the equalizer circuit. As the equalizing factor EQ is changed in 8 steps from 0 (i.e., 0x0 in hexadecimal form) to 7 (i.e., 0x7 in hexadecimal form), the gain of lower frequency components inclusive of the direct current component may be lowered while maintaining the gain of higher frequency components. Namely, the equalizer circuit of FIG. 3 has the function to amplify frequency components more in higher frequencies than in lower frequencies. Data passing through a transmission line or the like may end up having reduced high frequency components. An equalizer circuit having the frequency characteristics as illustrated in FIG. 4 may be used to correct a received waveform by compensating for losses along the transmission line (i.e., attenuation in high frequency components).
In the configuration illustrated in FIG. 3, the equalizing factor EQ applied to the equalizer circuit may be adjusted in response to the characteristics of the transmission line, thereby ensuring a sufficient data amplitude that is properly receivable despite changes in the characteristics of the transmission line. Adaptive equalization is a technology that changes the equalizing factor EQ in response to changes in the characteristics of the transmission line.
FIG. 5 is a drawing for explaining the concept of adaptive equalization. As illustrated in FIG. 5, a data waveform transmitted by a transmitter circuit 20 and having propagated through the transmission line 10 has waveform such as an eye pattern 40A. The eye pattern is observed when a single data signal having “0”s and “1”s appearing in a random manner is superimposed on itself multiple times for a period of several cycles. This data signal includes jitters caused by propagation through a transmission line, so that the timing of 0/1-signal-level transition is not aligned with predetermined timing (i.e., the timing synchronized with a clock signal). Because of this, the multiple superimposition of such a data signal for a period of several cycles results in signal waveforms with timing fluctuation being superimposed on one another, so that multiple trace lines appear at the positions of signal level transition as shown in the eye pattern 40A.
The eye pattern 40A is a data signal waveform observed when the temperature of the transmission line 10 is −20 degrees Celsius, for example. As the temperature of the transmission line 10 increases to 85 degrees Celsius, for example, the data signal waveform changes to an eye pattern 40B due to changes in the transmission line characteristics. Even when the transmission line characteristics are changed due to changes in the temperature of the transmission line 10, the use of adaptive equalization technology obtains a proper output from the equalizer circuit 12 by changing the equalizing factors of the equalizer circuit 12 (or the equalizing circuit of FIG. 3). Namely, the data signal waveform on the input side of the equalizer circuit 12 may significantly change from the eye pattern 40A to the eye pattern 40B. Despite such a change, automatic adaptive control may ensure that a data signal waveform on the output side of the equalizer circuit 12 exhibits almost no change from an eye pattern 41A to an eye pattern 41B. In this manner, properly receivable data amplitude may be automatically ensured with respect to the equalizer circuit 12.
FIG. 6 is a drawing illustrating an example of the configuration of an adaptive equalizer circuit using the equalizer circuit 12 of FIG. 1. In FIG. 6, the same elements as those of FIG. 1 are referred to by the same numerals.
The adaptive equalizer circuit of FIG. 6 includes a receiver circuit 50, an adaptive equalization logic 51, and a matrix 52. A data waveform transmitted by the transmitter circuit 20 and having propagated through the transmission line 10 is received by the receiver circuit 50. The adaptive equalization logic 51 derives equalizing factors by use of an algorithm utilizing the method of least squares.
The receiver circuit 50 includes the equalizer circuit 12, an analog-to-digital converter (ADC) 61, a data detecting circuit 62, and a demultiplexer 63. The adaptive equalization logic 51 includes a convolution computing circuit 64, a correlation and error computing circuit 65, a multiplier 66, a buffer 67, and an integrator 68.
According to the method of least squares, a difference between an output amplitude y of the receiver circuit 50 and an expected amplitude d is computed by the correlation and error computing circuit 65 as an error amplitude e, and feedback control is performed to minimize the mean squares of the error e. In order to bring the mean squares of the error amplitude e close to zero, the error amplitude e may need to be made uncorrelated with input amplitudes F0, F1, and F2 for the respective equalizing factors that are to be adjusted. In this manner, the principle of adaptive equalization is clear. When adaptive equalization is to be implemented as LSI, a digital region is generally employed for such implementation as digital implementation is suitable for LSI.
In the configuration illustrated in FIG. 6, the output amplitude of the equalizer circuit 12 is converted into a digital code by the analog-to-digital converter (ADC) 61 in order to achieve adaptive equalization in a digital region. In order to obtain the error amplitude e with respect to the digital code output of the ADC, the expected amplitude d may be multiplied by an output logic value (i.e., +1/−1) of the data detecting circuit 62, and, then, a difference between the resulting product and the digital code may be obtained. In so doing, the input and output latency of the analog-to-digital converter 61 may need to be taken into consideration. To this end, there may be a need to identify which bits contained in the demultiplexer data (i.e., the output of the demultiplexer 63) correspond to the ADC output digital code. The correlation and error computing circuit 65 performs correlation computation to select one-bit data corresponding to the ADC output digital code from the N-bit demultiplexer data. Namely, correlation between each bit of the demultiplexer data and the ADC output digital code is computed to select one-bit data that exhibits the highest correlation.
When an adaptive equalizer circuit is implemented as LSI, timing alignment as described above brings about increases in circuit size and power consumption. For example, the size of the correlation and error computing circuit 65 for performing timing alignment may be so big as to occupy half the circuit area of the adaptive equalization logic 51 illustrated in FIG. 6. In this manner, the adaptive equalizer circuit as illustrated in FIG. 6 has a problem in that its circuit size and power consumption are large.
Moreover, the adaptive equalizer circuit of FIG. 6 derives input amplitudes F0, F1, and F2 through computation by the convolution computing circuit 64. The matrix 52 is matrix data reflecting the transmission line characteristics. Convolution between the matrix 52 and the demultiplexer data is performed to estimate the input amplitudes F0, F1, and F2. The matrix 52 may be obtained by acquiring a unit-pulse-response waveform with respect to each of the transmission line 10 and the elements 13 through 15 of the equalizer circuit 12, followed by quantizing the obtained unit-pulse-response waveforms. The size of the matrix 52 is determined by the length of an inter-symbol interference component of the transmission line 10.
As described above, the adaptive equalizer circuit as illustrated in FIG. 6 may need to be provided in advance with the matrix 52 responsive to the transmission line characteristics. A different matrix 52 is thus provided for each different transmission line for which the equalizer circuit is to be used. Preparation of such matrixes requires a large amount of time and labor.
FIG. 7 is a drawing illustrating an example of the configuration of an adaptive equalizer circuit using the equalizer circuit of FIG. 2. This circuit of FIG. 7 is disclosed in Patent Document 1.
An adaptive equalizer circuit 100 of FIG. 7 includes an equalizer circuit 70, a data detecting circuit 71, a boundary detecting circuit 72, a demultiplexer 73, a clock recovery unit (CRU) 74, a phase interpolator circuit (PI) 75, a monitor unit 76, and a control unit 77. The equalizer circuit 70 has the configuration illustrated in FIG. 3. The phase interpolator circuit 75 generates two clock signals having a predetermined phase difference (e.g., 90 degrees) from each other based on a predetermined reference clock signal. One of the clock signals is supplied to the data detecting circuit 71, and the remaining one of the clock signals is supplied to the boundary detecting circuit 72.
The data detecting circuit 71 and the boundary detecting circuit 72 detect HIGH/LOW of the output signal of the equalizer circuit 70 at the edge timings of the respective clock signals supplied thereto. +1 may be output in response to HIGH detection, and −1 may be output in response to LOW detection. The phases of the clock signals supplied from the phase interpolator circuit 75 are controlled such that the data detecting circuit 71 performs signal detection at data centers, and the boundary detecting circuit 72 performs signal detection at data boundaries.
The clock recovery unit 74 includes a phase detector PD for detecting the phases of the outputs of the data detecting circuit 71 and boundary detecting circuit 72, and further includes a low-pass filter LPF for temporally integrating the phase detection results of the phase detector PD. The output of the low-pass filter LPF is applied to the phase interpolator circuit 75 as a signal for controlling the clock signals output from the phase interpolator circuit 75.
When data detection and boundary detection are performed at correct timings, the output of the boundary detecting circuit 72 assumes +1 or −1 with equal probability at the point of a data change between 0 and 1 regardless of the immediately preceding data detection value of the data detecting circuit 71. An integrated value of the output of the boundary detecting circuit 72 is thus substantially constant when data detection and boundary detection are performed at correct timings.
When data detection and boundary detection are not performed at correct timings, the output of the boundary detecting circuit 72 at the point of a data change between 0 and 1 is correlated with the immediately preceding output of the data detecting circuit 71. When the timing of the clock signals is earlier than expected, the output of the boundary detecting circuit 72 at the point of a data change between 0 and 1 is +1 (or −1) that is always at the same phase as +1 (or −1) of the immediately preceding data detection output of the data detecting circuit 71. When the timing of the clock signals is later than expected, the output of the boundary detecting circuit 72 at the point of a data change between 0 and 1 is −1 (or +1) that is always at the opposite phase from +1 (or −1) of the immediately preceding data detection output of the data detecting circuit 71. Determination may be made as to whether the timing of the clock signals is too early or too late in response to the phases of the outputs of the data detecting circuit 71 and boundary detecting circuit 72 detected by the phase detector PD. Then, the phase and frequency of the clock signals may be adjusted in response to the result of the determination thereby to generate proper clock signals that are synchronized with the received signal.
In the adaptive equalizer circuit 100 of FIG. 7, the monitor unit 76 and control unit 77 play a central role in adaptive equalization. The distribution of output logic values of the boundary detecting circuit 72 is analyzed in order to derive an equalizing factor applied to the equalizer circuit 70. A trigger signal generator 81 of the monitor unit 76 generates a trigger signal when the output of the data detecting circuit 71 is a particular pattern such as 1101, 1001, 0101, etc. In response to the trigger signal, an integrator 82 integrates the output logic values of the boundary detecting circuit 72 separately for each of the above-noted patterns.
The amount of phase variation in the data input into the data detecting circuit 71 changes in response to past data. When the above-noted patterns such as 1101, 1001, and 0101 are input, thus, the amount of phase variation with respect to the second half “01” differs depending on the first half “11”, “10”, and “01” that are past data. The histogram of phase variation amounts may fit to a normal distribution. In such a case, the relationship between output values and sample timings for data detection assumes a linear relation with respect to the values obtained through integration by the integrator 82. Based on this relationship, the control unit 77 estimates the amount of phase variation, and adjusts the equalizing factor of the equalizer circuit 70 to minimize the estimated amount of phase variation.
In the configuration illustrated in FIG. 7, the distribution of boundary data necessary to implement clock data recovery (CDR), which is one of the main functions of existing data receiver circuits, is analyzed to adjust an equalizing factor to its optimum value. The merit is that an existing circuit for CDR can be utilized. On the other hand, processing performed in the monitor unit 76 and the control unit 77 is complicated, requiring complex circuits. Further, the amount of phase variation may not properly fit to a normal distribution. There is thus a possibility that an optimum equalizing factor cannot be derived.    [Patent Document 1] Japanese Patent Application Publication No. 2005-303607